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2.0 Internal User-Programmable Registers (Continued)
Note 22: LM12454 (Refer to
Table 2).
Note 23: LM12(H)458 only. Must be set to “0” for the LM12454.
A4
A3
A2
A1
A0
Purpose
Type
D7
D6
D5
D4
D3
D2
D1
D0
000
Instruction
RAM
(RAM
Pointer =
00)
R/W
VIN
(MUXOUT) (Note 22)
VIN+
(MUXOUT+) (Note 22)
0to0
Pause
Loop
111
0
R/W
Watch-
0
to
1
Acquisition Time
dog
8/12
Timer
Sync
111
000
Instruction
RAM
(RAM
Pointer =
01)
R/W
0
to
0
Comparison Limit #1
111
000
R/W
0
to
1
Don’t Care
>/<
Sign
111
000
Instruction
RAM
(RAM
Pointer =
10)
R/W
0
to
0
Comparison Limit #2
111
000
R/W
0
to
1
Don’t Care
>/<
Sign
111
10000
Configuration
Register
R/W
I/O
Auto
Chan
Stand-
Full
Auto-
Reset
Start
Sel
Zeroec
Mask
by
Cal
Zero
10001
R/W
Don’t Care
DIAG
(Note
23)
Test =
0
RAM Pointer
10010
Interrupt
Enable
Register
R/W
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
10011
R/W
Number of Conversions in Conversion
Sequencer Address to
FIFO to Generate INT2
Generate INT1
10100
Interrupt
Status
Register
R
INST7
INST6
INST5
INST4
INST3
INST2
INST1
INST0
10101
R
Actual Number of Conversions Results
Address of Sequencer
in Conversion FIFO
Instruction
being Executed
10110
Timer
Register
R/W
Timer Preset: Low Byte
10111
R/W
Timer Preset: High Byte
11000
Conversion
FIFO
R
Conversion Data: LSBs
11001
R
Address or Sign
Sign
Conversion Data: MSBs
11010
Limit Status
Register
R
Limit #1 Status
11011
R
Limit #2 Status
FIGURE 14. LM12(H)454/8 Memory Map for 8-Bit Wide Databus (BW = “1” and Test Bit = “0”)
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